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general description the ds1337 serial real - time clock is a low - power clock/calendar with two programmable time - of - day alarms and a programmable square - wave output. address and data are transferred serially through an i 2 c bus. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24 - hour or 12 - hou r format with am/pm indicator. the device is fully accessible through the serial interface while v cc is between 1.8v and 5.5v. i 2 c operation is not guaranteed below 1.8v. timekeeping operation is maintained with v cc as low as 1.3v. applications handheld s (gps, pos terminal, mp3 player) consumer electronics (set - top box, vcr/digital recording) office equipment (fax/printer, copier) medical (glucometer, medicine dispenser) telecommunications (router, switch, server) other (utility meter, vending machine, t hermostat, modem) typical operating circuit benefits and features ? completely manages all timekeeping functions o real - time clock (rtc) counts seconds, minutes, hours, day, date, month, and year with leap - year compensation valid up to 2100 o two time - of - day alarms o programma ble sq uare - wave output defaults to 32khz on power - up o oscillator stop flag ? interfaces with most microcontrollers o i 2 c serial interface ? s urface - mount package with an integrated crystal (dc1337c) saves additional space and simplifies design ? - 40 c to +85 c industrial temperature range supports o peration in a wide range of applications ordering information part temp range pin - packa ge top mark ? ds1337+ - 40c to +85c 8 dip (300 mils) ds1337 ds1337s+ - 40c to +85c 8 so (150 mils) ds1337 ds1337u+ - 40c to +85c 8 sop 1337 ds1337c# - 40c to +85c 16 so (300 mils) ds1337c + denotes a lead (pb) - free/rohs - compliant device. # denotes a rohs - compliant device that may include lead that is exempt under the rohs requirements. the lead finish is jesd97 category e3, and is compatible with both lead - based and lead - free soldering processes. ? a + anywhere on the top mark denotes a lead - free device. a # denotes a rohs - compliant device. pin configurations appear at end of data sheet. 19 - 4652; 4/ 15 ds1337 i 2 c serial real - time clock 1 of 16 note: some revisions of this device may incorporate deviations from published specifications kno wn as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata , go to: www.maxim - ic.com/errata . downloaded from: http:///
ds1337 i 2 c serial real - time clock absolute maximum ratings voltage range on any pin relative to ground... - 0.3v to +6.0v operating temperature range (noncondensing) .- 40c to +85c storage temperature range.. - 55c to +125c soldering temperaturesee ipc/jedec j - std - 020 specification stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affec t device reliability. recommended dc operating conditions (t a = - 40c to +85c) parameter symbol conditions min typ max units v cc supply voltage v cc full operation 1.8 3.3 5.5 v v cct timekeeping (note 5) 1.3 1.8 v logic 1 v ih scl, sda 0.7 x v cc v cc + 0.3 v inta , sqw/ intb 5.5 logic 0 v il - 0.3 +0.3 x v cc v dc electrical characteristicsfull operation ( v cc = 1.8v to 5.5v , t a = - 40c to +85c.) (note 1) parameter symbol conditions min typ max units input leakage i li (note 2) -1 +1 a i/o leakage i lo (note 3) -1 +1 a logic 0 output (v ol = 0.4v) i ol (note 3) 3 ma active supply current i cca (note 4) 150 a standby current i ccs (notes 5, 6) 1.5 a dc electrical characteristics -- timekeeping ( v cc = 1.3v to 1.8v, t a = - 40c to +85c .) (note 1) parameter symbol conditions min typ max units timekeeping current (oscillator enabled) i cctosc (notes 5, 7, 8, 9) 425 600 na data - retention current (oscillator disabled) i cctddr (notes 5, 9) 100 na 2 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock ac electrical characteristics (v cc = 1.8v to 5.5v, t a = - 40c to +85c.) (note 1) parameter symbol conditions min typ max units scl clock frequency f scl fast mode 100 400 khz standard mode 0 100 bus free time between a stop and start c ondition t buf fast mode 1.3 s standard mode 4.7 hold time (repeated) start condition (note 10) t hd:sta fast mode 0.6 s standard mode 4.0 low period of scl clock t low fast mode 1.3 s standard mode 4.7 high period of scl clock t high fast mode 0.6 s standard mode 4.0 setup time for a repeated start condition t su:sta fast mode 0.6 s standard mode 4.7 data hold time (notes 11, 12) t hd:dat fast mode 0 0.9 s standard mode 0 data setup time (note 13) t su:dat fast mode 100 ns standard mode 250 rise time of both sda and scl signals (note 14) t r fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 1000 fall time of both sda and scl signals (note 14) t f fast mode 20 + 0.1c b 300 ns standard m ode 20 + 0.1c b 300 setup time for stop condition t su:sto fast mode 0.6 s standard mode 4.0 capacitive load for each bus line c b (note 14) 400 pf i/o capacitance (sda, scl) c i/o (note 15) 10 pf oscillator stop flag (osf) delay t osf 100 ms note 1: limits at - 40c are guaranteed by design and are not production tested. note 2: scl only. note 3: sda, inta , and sqw/ intb . note 4: i cca scl clocking at max frequency = 400khz, v il = 0.0v, v ih = v cc. note 5: specified with the i 2 c bus inac tive, v il = 0.0v, v ih = v cc. note 6: sqw enabled. note 7: specified with the sqw function disabled by setting intcn = 1. note 8: using recommended crystal on x1 and x2. note 9: the device is fully accessible when 1.8 v cc 5.5v. time and date are maintained when 1.3v v cc 1.8v. note 10: after this period, the first clock pulse is generated note 11: a device must internally provide a hold time of at least 300ns for the sda signal (refer red to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 12: the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 13: a fast - mode device can be used in a standard - mode system, but the requirement t su:dat to 25 0ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 14: c b total capacitance of one bus line in pf. note 15: guaranteed by design. not production tested. 3 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock note 16: the parameter t osf is the period of time that the oscillator must be stopped for the osf b it to be set over the voltage range of v cc(min) v cc v cc(max). . typical operating characteristics (v cc = 3.3v, t a = +25c, unless otherwise noted.) i cca vs. v cc 0 25 50 75 100 125 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) i cc (ua) i cc vs. v cc 300 400 500 600 700 800 900 1000 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) i cc (na) intcn = 0 (squarew ave on) intcn = 1 (squarew ave off) i cct osc i ccs i ccs vs. temperature 350 400 450 500 550 600 650 700 -40.0 -20.0 0.0 20.0 40.0 60.0 80.0 v cc (v) i cc (na) intcn = 0 (squarew ave on) v cc = 3.0v intcn = 1 (squarew ave off) oscillator frequency vs. v cc 32768 32768.05 32768.1 32768.15 32768.2 32768.25 32768.3 32768.35 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 v cc (v) frequency (hz) 4 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock pin description pin name function 8 16 1 x1 connections for a standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 6pf. for more information about crystal selection and crystal layout considerations, refer to application note 58: crystal consi derations with dallas real - time clocks . an external 32.768khz oscillator can also drive the ds1337. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated. 2 x2 3 14 inta interrupt output. when enabl ed, inta is asserted low when the time/day/date matches the values set in the alarm registers. this pin is an open - drain output and requires an external pullup resistor. t he pull up voltage may be up to 5.5v, regardless of the voltage on v cc . if not used, this pin may be left floating. 4 15 gnd ground. dc power is provided to the device on this pin. 5 16 sda serial data input/output. sda is the input/output pin for the i 2 c serial interface. the sda pin is open - drain output and requires an external pullup resistor. 6 1 scl serial clock input. scl is used to synchronize data movement on the serial interface. 7 2 s qw/ intb square - wave/interrupt output. programmable square - wave or interrupt output signal. it is an open - drain output and requires an external pullup resistor. the pull up voltage may be up to 5.5v, regardless of the voltage on v cc . if not used, this pin may be left floating. 8 3 v cc dc power. dc power is provided to the device on this pin. 4C 13 n.c. no connect. these pins are not connected internally, but must be grounded for proper operation. timing diagram 5 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock block diagr am detailed description the block diagram shows the main elements of the ds1337. as shown, communications to and from the ds1337 occur serially over an i 2 c bus. the ds1337 operates as a slave device on the serial bus. access is obtained by implementing a start condition and providing a device identification code, fol lowed by data. subsequent registers can be accessed sequentially until a stop condition is executed. t he device is fully accessible through the i 2 c interface whenev er v cc is between 5.5v and 1.8v. i 2 c operation is not guaranteed when v cc is below 1.8v. the ds1337 maintains the time and date when v cc is as low as 1.3v. oscillator circuit the ds1337 uses an external 32.768khz crystal. the oscillator circuit does not require any external resistors or capacitors to operate. table 1 specifies several crystal parameters for the external crystal. the block diagram shows a functional schematic of the oscillator circuit. the startup time i s usually less than 1 second when using a crystal with the specified characteristics. table 1 . crystal specifications* parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 50 k ? load capacitance c l 6 pf *the crystal, traces, and crystal input pins should be isolated from rf generating signals . refer to application note 58: crystal considerations for dallas real - time clocks for additional specifications. 6 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock clock accuracy the accuracy of the clock is dependent upon the accuracy of the crystal and th e accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the cryst al was trimmed . crystal frequency drift caused by temperature shifts creates additional error. external circuit noi se coupled into the oscillator circuit can result in the clock running fast. figure 1 shows a typical pc board layout for isolating the crystal and oscillator from noise. refer to appli cation note 58: crystal considerations with dallas real - time clocks for detailed information. figure 1 . typical pc board layout for crystal ds1337c only the ds1337c integrates a standard 32,768hz crystal in the package. typical accuracy at nominal v cc and +25c is approximately +10ppm. refer to application note 58 for information about crystal accuracy vs. temperature. operating modes the amount of current consumed by the ds1337 is determined, in part, by the i 2 c interface and oscillator operation. the following table shows the relationship between the operating mode and the corresponding i cc parameter. operating mode v cc power i 2 c interface active 1.8v v cc 5.5v i cc active (i cca ) i 2 c interface inactive 1.8v v cc 5.5v i cc standby (i ccs ) i 2 c interface inactive 1.3v v cc 1.8v timekeeping (i cctosc ) i 2 c interface inactive oscillator disabled 1.3v v cc 1.8v data retention (i cctddr ) local ground plane (layer 2) crystal x1 x2 gnd note: avoid routing signals in the crosshatched area (upper left - hand quadrant) of the package unless there is a ground plane between the signal line and the package. 7 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock addres s map table 2 shows the address map for the ds1337 registers. during a multibyte access, when t he address pointer reaches the end of the register space (0fh) it wraps around to location 00h. on an i 2 c start, stop, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. t he time information is read from these secondary registers, while the clock may cont inue to run. this eliminates the need to re - read the registers in case of an update of the main registers during a read. table 2 . timekeeper registers address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h 0 10 seconds seconds seconds 00 C 59 01h 0 10 minutes minu tes minutes 00 C 59 02h 0 12/ 24 am /pm 10 hour hour hours 1C 12 +am/pm 00 C 23 10 hour 03h 0 0 0 0 0 day day 1C7 04h 0 0 10 date date date 01 C 31 05h century 0 0 10 month month month/ century 01 C 12 + century 06h 10 year year year 00 C 99 07h a1m1 10 s econds seconds alarm 1 seconds 00 C 59 08h a1m2 10 minutes minutes alarm 1 minutes 00 C 59 09h a1m3 12/ 24 am /pm 10 hour hour alarm 1 hours 1C 12 + am/pm 00 C 23 10 hour 0ah a1m4 dy/ dt 10 date day alarm 1 day 1C7 date alarm 1 date 01 C 31 0bh a2m2 10 minutes minutes alarm 2 minutes 00 C 59 0ch a2m3 12/ 24 am /pm 10 hour hour alarm 2 hours 1C 12 + am/pm 00 C 23 10 hour 0dh a2m4 dy/ dt 10 date day alarm 2 day 1C7 date alarm 2 date 01 C 31 0eh eosc 0 0 rs2 rs1 intcn a2ie a1ie control 0fh osf 0 0 0 0 0 a2f a1f status note: unless otherwise specified, the state of the registers is not defined when power is first applied or v cc falls below the v osc . i 2 c interface the i 2 c interface is accessible whenever v cc is at a valid level. if a microcontroller connected to the ds1337 resets while reading from the ds1337 during an i 2 c read, the two could become unsynchronized. the microcontroller must terminate the last byte read with a not - acknowledge (nack) to properly terminate the read. when the micr ocontroller resets, the ds1337 i 2 c interface may be placed into a known state by toggling scl until sda i s observed to be at a high level. at that point the microcontroller should pull sda low while scl is high, generating a start condition. 8 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock clock and cal endar the time and calendar information is obtained by reading the appropriate register bytes. the rtc regist ers are illustrated in table 2 . the time and calendar are set or initialized by writing the appropriate register bytes . the contents of the time and calendar registers are in the binary - coded decimal (bcd) format. the day - of - week register increments at midnight. values that correspond to the day of week ar e user - defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on.). illogical t ime and date entries result in undefined operation. when reading or writing the time and date registers, secondary (user) buffers are used to prevent err ors when the internal registers update. when reading the time and date registers, the user buffers are synchroni zed to the internal registers on any start or stop and when the register pointer rolls over to zero. the countdown chain is reset whenever the seconds register is written. wr ite transfers occur on the acknowledge pulse from the device. to avoid rollover issues, once the countdown chain is re set, the remaining time and date registers must be written within 1 second. the 1hz square - wave output, if enable, transitions high 500ms after the seconds data transfer, provided the oscillator is already running. the ds1337 can be run in either 12 - hour or 24 - hour mode. bit 6 of the hours register is defined as the 12 - or 24 - hour mode - select bit. when high, the 12 - hour mode is selected. in the 12 - hour mode, bit 5 is the am /pm bit with logic high being pm. in the 24 - hour mode, bit 5 is the second 10 - hour bit (20 C 23 hours). all hours values, including the alarms, must be reinitialized whenever the 12/ 24 - hour mode bit is changed. the century bit (bit 7 of the month register) is toggled when the years register overflows from 99 C 00. alarms the ds1337 contains two time - of - day/date alarms. alarm 1 can be set by writing to registers 07h C 0ah. alarm 2 can be set by writing to registers 0bh C 0dh. the alarms can be programmed (by the intcn bit of the control register) to operate in two different modes each alarm can drive its own separate interrupt output or both alarms can drive a common interrupt output. bit 7 of each of the time - of - day/date alarm registers are mask bits ( table 2 ). when all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeepi ng registers 00h C 06h match the values stored in the time - of - day/date alarm registers. the alarms can also be programmed to repeat every second, minute, hour, day, or date. table 3 shows the possible settings. configurations not listed in the table result in illogical operation. the dy/ dt bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 C 5 of that register reflects the day of the week or the date of the month. if dy/ dt is written to logic 0, the alarm is the result of a match with date of the month. if dy/ dt is written to logic 1, the alarm is the result of a match with day of the week. when the rtc register values match alarm register settings, the correspondi ng alarm flag (a1f or a2f) bit is set to logic 1. the bit(s) will remain at a logic 1 until written to a logic 0 by the user. if the corresponding alarm interrupt enable (a1ie or a2ie) is also set to logic 1, the alarm condition activates one of the interr upt output ( inta or sqw/ intb ) signals. the match is tested on the once - per -s econd update of the time and date registers. 9 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock table 3 . alarm mask bits dy/ dt alarm 1 register mask bits (bit 7) alarm rate a1m4 a1m3 a1m2 a1m1 x 1 1 1 1 alarm once per second x 1 1 1 0 alarm when seconds match x 1 1 0 0 alarm when minutes and seconds match x 1 0 0 0 alarm when hours, minutes, and seconds match 0 0 0 0 0 alarm when date, hours, minutes, and seconds match 1 0 0 0 0 alarm when day, hours, minutes, and seconds match dy/ dt alarm 2 register mask bits (bit 7) ala rm rate a2m4 a2m3 a2m2 x 1 1 1 alarm once per minute (00 seconds of every minute) x 1 1 0 alarm when minutes match x 1 0 0 alarm when hours and minutes match 0 0 0 0 alarm when date, hours, and minutes match 1 0 0 0 alarm when day, hours, and minutes match special-purpose registers the ds1337 has two additional registers (control and status) that control the rtc, alarms, and s quare - wave output. control register (0eh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc 0 0 rs2 rs1 intcn a2ie a1 ie bit 7: enable oscillator (e o sc ). this active - low bit when set to logic 0 starts the oscillator. when this bit is set to logic 1, the oscillator is stopped. this bit is enabled (logic 0) when power is fir st applied. bits 4 and 3: rate select (rs2 and rs1). these bits control the frequency of the square - wave output when the square wave has been enabled. the table below shows the square - wave frequencies that can be selected with the rs bits. these bits are both set to logic 1 (32khz) when power is first applied. sqw/ i n tb output intcn rs2 rs1 sqw/ i n tb output a2ie 0 0 0 1hz x 0 0 1 4.096khz x 0 1 0 8.192khz x 0 1 1 32.768khz x 1 x x a2f 1 bit 2: interrupt control (intcn). this bit controls the relationship between the two alarms and the interrupt o utput pins. when the intcn bit is set to logic 1, a match between the timekeeping re gisters and the alarm 1 registers l activates the inta pin (provided that the alarm is enabled) and a match between the timekeeping registers and the alarm 2 registers activates the sqw/ intb pin (provided that the alarm is enabled). when the intcn bit is set to logic 0, a square wave is output on the sqw/ intb pin. this bit is set to logic 0 when power is first applied. 10 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock bit 1: alarm 2 interrupt enable (a2ie). when set to logic 1, this bit permits the alarm 2 flag (a2f) bit in the status register to assert inta (when intcn = 0) or to assert sqw/ intb (when intcn = 1). when the a2ie bit is set to logic 0, the a2f bit does not initiate an interrupt signal. the a2ie bit is disab led (logic 0) when power is first applied. bit 0: alarm 1 interrupt enable (a1ie). when set to logic 1, this bit permits the alarm 1 flag (a1f) bit in the status register to assert inta . when the a1ie bit is set to logic 0, the a1f bit does not initiate t he inta signal. the a1ie bit is disabled (logic 0) when power is first applied. status register (0fh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 osf 0 0 0 0 0 a2f a1f bit 7: oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and calendar data. this bit is set to logic 1 anytime that the oscillator stops. the following are examples of conditions that can cause the osf bit to be set: 1) the first time power is applied. 2) the voltage present on v cc is insufficient to support oscillation. 3) the eosc bit is turned off. 4) external influences on the crystal (e.g., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0. bit 1: alarm 2 flag (a2f). a logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. this flag can be used to generate an interrupt on either inta or sqw / intb depending on the status of the intcn bit in the control register. if the intcn bit is set to logic 0 an d a2f is at logic 1 (and a2ie bit is also logic 1), the inta pin goes low. if the intcn bit is set to logic 1 and a2f is logic 1 (and a2ie bit is also logic 1), the sqw/ intb pin goes low. a2f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. bit 0: alarm 1 flag (a1f). a logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. if the a1ie bit i s also logic 1, the inta pin goes low. a1f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. 11 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock i 2 c serial data bus the ds1337 supports the i 2 c bus protocol. a device that s ends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a master. the devices t hat are controlled by the master are referred to as slaves. a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions must control the bus. the ds1337 opera tes as a slave on the i 2 c bus. within the bus specifications a standard mode (100khz maximum clock rate) and a fast mode (400k hz maximum clock rate) are defined. the ds1337 works in both modes. connecti ons to the bus are made through the open - drain i/o lines sda and scl. the following bus protocol has been defined ( figure 2 ): ? da ta transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high . changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a cha nge in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start conditi on, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions are not limited, and are determined by the master device. the information is transferred byte - wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addre ssed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this ack nowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge - related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an ackno wledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the dat a line high to enable the master to generate the stop condition. 12 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock figure 2 . data transfer on i 2 c serial bus depending upon the state of the r/ w bit, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each receiv ed byte. data is transferred with the most significant bit (msb) first. 2) data transfer from a slave transmitter to a master receiver. the master transmits the first byte (the slave address). the slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. the master returns an acknowledge bit after all received bytes other than the last byte . at the end of the last received byte, a not acknowledge is returned. the master device generat es all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop conditi on or with a repeated start condition. since a repeated start condition is also the beginning of the next serial tr ansfer, the bus is not released. data is transferred with the most significant bit (msb) first. the ds1337 can operate in the following two modes: 1) slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start and stop conditions are recogni zed as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit ( figure 3 ). the slave address byte is the first byte received after the master generates the start condition. the slave address byte contains the 7 - bit ds1337 address, which is 1101000, followed by the direction bit (r/ w ), which, for a write, is 0. after receiving and decoding the slave address byte the device outputs an acknowledge on the sda line. after the ds1337 acknowledges the slave address + write bit, the master transmits a register address to the ds1337. this sets the register pointer on the ds1337. the master may then transmit zero or more bytes of data, with the ds1337 acknowledging each byte receiv ed. the address pointer will increment after each data byte is transferred. the master generates a stop condition to terminate the data write. 2) slave transmi tter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer dir ection is reversed. serial data is transmitted on sda by the ds1337 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfe r ( figure 4 and figure 5 ). the slave address byte is t he first byte received after the master generates a start condition. the slave addr ess byte contains the 7 - bit ds1337 address, which is 1101000, followed by the direction bit (r/ w ), which, for a read, is 1. after receiving and decoding the slave address byte the device outputs an acknowledge on the sda line. the ds1337 then begins to transmit data starting with the register address pointed to by the register pointer. if the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. the ds1337 must receive a not acknowledge to end a read. 13 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock figure 3 . data write slave receiver mode figure 4 . data read (from cu rrent pointer location) slave transmitter mode figure 5 . data read (write pointer, then read) slave receive and transmit ... a xxxxxxxx a s 0 xxxxxxxx a xxxxxxxx a xxxxxxxx a p s - start a - acknowledge (ack) p - stop data transferred (x+1 bytes + acknowledge) 1101000 master to slave slave to master ... a xxxxxxxx a 1101000 s 1 xxxxxxxx a xxxxxxxx xxxxxxxx a p a s - start a - acknowledge (ack) p - stop a - not acknowledge (nack) data transferred (x+1 bytes + acknowledge) note: last data byte is followed by a nack master to slave slave to master ... a xxxxxxxx xxxxxxxx a xxxxxxxx a xxxxxxxx a p s - start sr - repeated start a - acknowledge (ack) p - stop a - not acknowledge (nack) data transferred (x+1 bytes + acknowledge) note: last data byte is followed by a nack a xxxxxxxx a 1101000 s 0 a 1101000 sr 1 master to slave slave to master 14 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock handling, pc board l ayout, and assembly the ds1337c package contains a quartz tuning - fork crysta l. pick - and - place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. ultrasonic c leaning should be avoided to prevent damage to the crystal. avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. all n.c. (no connect) pins must be connected to ground. moisture - sensitive packages are shipped from the factory dry - packed. handling instructions listed on the package label must be followed to prevent damage during reflow. refer to the ipc/jedec j - std - 020 standard for moisture - sensitive device (msd) classifications. pin configurations chip information transistor count: 10,950 process: cmos thermal information package theta -j a (c/w) the ta -j c (c/w) 8 dip 110 40 8 so 170 40 8 sop 229 39 16 so 73 23 package information for the latest package outline information and land patterns, go to www.maxim - ic.com/packages . package type package c ode document no. 8 pdip p8+8 21 - 0043 8 so s8+2 21 - 0 041 8 ? max u8+1 21 - 0036 16 so w16 - h2 21 - 0042 top view dip inta x1 x2 gnd v cc scl sda sqw / intb ds1337 so, sop x1 x2 gnd v cc scl sda sqw / intb inta ds1337 sqw/ intb scl sda gnd inta v cc n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. ds1337c so (300 mils) 15 of 16 downloaded from: http:///
ds1337 i 2 c serial real - time clock revision history revision date description pages changed 080508 added device access details to general description section. 1 removed leaded ordering numbers from the ordering information table. 1 added note 5 to timekeeping v cc ec table range. 2 added full operation and timekeeping to headers to clarify table usage. 2 added osf parameter to ec table. 3 updated pin description to indicate max input voltage and that unused outputs may be left open. 5 added oscillator circuit and show open - drain transistors on block diagram . 6 added operating mode section with details on operating mode and corresponding icc parameter. 7 added i 2 c interface section explaining how to synchronize a mi crocontroller and the rtc. 8 corrected legend in figure 5 for not - acknowledge (add overbar to symbol). 14 071609 removed conflicting sda/scl input bias statement in pin description . 5 042315 revised benefits and features section 1 16 of 16 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirel y embodied in a maxim product. no circuit pat ent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 1 60 r io robles , s a n jose , ca 9 5134 408 - 601 - 1000 ? 2015 maxim integrated products the maxim logo is a registered trademark of maxim integrated products, inc. downloaded from: http:///

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